7of9 @7of9@fedibird.com

#PYNQ_flow #dma
Running FFT with axi dma channel wait “DMA channel not started”
https://discuss.pynq.io/t/running-fft-with-axi-dma-channel-wait-dma-channel-not-started/1479

#PYNQ_flow #Project
PYNQ community projects
http://www.pynq.io/embedded.html

#PYNQ_flow #DMA
DMA example design, how M_AXI_SG and M_AXI_S2MM are connected
https://forums.xilinx.com/t5/AXI-Infrastructure-Archive/DMA-example-design-how-M-AXI-SG-and-M-AXI-S2MM-are-connected/td-p/909589

M_AXI_SG
Scatter-Gather

#PYNQ_flow #IRQ

対処として

https://forums.xilinx.com/t5/Embedded-Linux/A-key-error-when-I-am-trying-to-access-a-DMA-IP-on-PYNQ-Z1-board/td-p/847817

- concatからIRQ_F2Pに直接接続しない
- AXI Interrupt Controllerを経由する

#PYNQ_flow #DMA
DMA irq ports cause python empty string dict lookup
https://github.com/Xilinx/PYNQ/issues/964

#PYNQ_flow #IRQ
IRQ_F2P

AR 51763
Zynq-7000 - PL から PS へ割り込み信号を接続するときの F2P_IRQ の IRQ ID# を確認する方法
https://japan.xilinx.com/support/answers/51763.html

#PYNQ_flow #DDR
Docs » PYNQ Libraries » DMA
v2.4
https://pynq.readthedocs.io/en/v2.4/pynq_libraries/dma.html

DigilentのPYNQ Imageと同じバージョン

#PYNQ_flow #DMA
PYNQ > FIFO loopbackを含むDMA転送のBlock Design (Vivado v2019.1) > v2017.2の方法から変更
https://qiita.com/7of9/items/de3f3b62bac9eda99352

#PYNQ_flow #AXI
AXI Interconnect (古い) または AXI SmartConnect (新しい)

#PYNQ_flow #DDR
Docs » PYNQ Libraries » DMA
https://pynq.readthedocs.io/en/v2.5.1/pynq_libraries/dma.html#dma

#PYNQ_flow #DDR
PYNQ を使って Python で手軽に FPGA を活用 (5)
https://www.acri.c.titech.ac.jp/wordpress/archives/36

BRAMを使う
AXI-DMAとは別かな

#PYNQ_flow #DDR

http://www.fpgadeveloper.com/2014/08/using-the-axi-dma-in-vivado.html

A. ポーリング
B. 割り込み

> Our software application will test the DMA in polling mode, but to be able to use it in interrupt mode, we need to connect the interrupts ‘mm2s_introut’ and ‘s2mm_introut’ to the Zynq PS.

#PYNQ_flow #keyword
http://www.fpgadeveloper.com/2014/08/using-the-axi-dma-in-vivado.html

Connect the Memory-mapped AXI buses
5.

S AXI HP0 interface
AXI high performance slave interface 0

#PYNQ_flow #DDR #keyword
http://www.fpgadeveloper.com/2014/08/using-the-axi-dma-in-vivado.html

> AXIS_MM2S and AXIS_S2MM are AXI4-streaming buses, which source and sink a continuous stream of data, without addresses.

#PYNQ_flow #DDR

上記の関連ビデオ
Using AXI DMA in Vivado Reloaded
http://www.fpgadeveloper.com/2017/10/using-axi-dma-in-vivado-reloaded.html

#PYNQ_flow #DDR
上記のリンクから

Using the AXI DMA in Vivado
http://www.fpgadeveloper.com/2014/08/using-the-axi-dma-in-vivado.html

AXI DMA使用のTutorial

#PYNQ_flow #DDR
Read and Write to DDR in Zed Board
http://zedboard.org/content/read-and-write-ddr-zed-board

64バイトは書き込めるけど、それ以上はどうするか
という質問

#PYNQ_flow #DDR
Zynq UltraScale+ MPSoC、PS DDR - DRAM のコンフィギュレーション モード レジスタを読み出す方法
https://japan.xilinx.com/support/answers/70166.html

Zynq UltraScale+ MPSoC, PS DDR - How do I read the DRAM's configuration mode registers?
https://www.xilinx.com/support/answers/70166.html

#pynq_flow
Digi-Key

2019-04-03
PythonとJupyter NotebookでFPGAベース設計の構築とプログラミングを迅速化
https://www.digikey.jp/ja/articles/build-and-program-fpga-based-designs-quickly-python-jupyter-notebooks

#PYNQ_flow #HDMI
2020-07-11 PYNQ > Jupyter NotebookでHDMIモニタにsine curveを描く (pynq.lib.video Module使用)
https://qiita.com/7of9/items/d1c72a1ae9fc731711c0