7of9 @7of9@fedibird.com

#PYNQ_flow #HDMI
2020-07-11 PYNQ > HDMI出力で線を引く (pynq.lib.video Moduleのwriteframe()使用 + frameのRGB値を変更)
https://qiita.com/7of9/items/21c528ec9991d2c1f544

#PYNQ_flow #HDMI
pynq.lib.video Module
https://pynq.readthedocs.io/en/v2.0/pynq_package/pynq.lib/pynq.lib.video.html

readframe()
readframe_async()

writeframe(frame)
writeframe_async(frame)

#PYNQ_flow #HDMI
HDMI FrameBuffer Example Design
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842753/HDMI+FrameBuffer+Example+Design
v2019.2, v2019.1 ... v2017.3
各バージョンごとのリンク

zipファイル申請でFAEの入力などが必要

#PYNQ_flow #HDMI
pynq.drivers package
https://pynq.readthedocs.io/en/v1.3/pynq.drivers.html
save_as_jpeg()などのAPIの説明

#PYNQ_flow #HDMI #keyword
HDCP
High-bandwidth Digital Content Protection
http://e-words.jp/w/HDCP.html

> 著作権で保護された映像コンテンツが表示装置へ伝送される間に不正にコピーされるのを防止する暗号化技術

#PYNQ_flow #xilinx #license
Core License Agreement
https://www.xilinx.com/products/intellectual-property/license/core-license-agreement.html

#PYNQ_flow #hdmi

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/33128528/HDMI+FrameBuffer+Example+Design+2018.3

> You will also require the HDMI IP Core evaluation license to build this design. You can request the IP evaluation license

#PYNQ_flow #hdmi
HDMI FrameBuffer Example Design 2018.3
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/33128528/HDMI+FrameBuffer+Example+Design+2018.3

ZCU102 Evaluation Boardでの例
PetaLinuxを使っている

#PYNQ_flow
AR♯ 61625
Video IP サンプル デザイン トップ ページ
https://japan.xilinx.com/support/answers/61625.html

AXI VDMA
Framebuffer Read
Framebuffer Write
などのサンプルデザイン

#PYNQ_flow #Vivado_flow #setup #vmware
VivadoをUbuntuの仮想環境に導入する
https://qiita.com/kawanon868/items/42ae3143014f4b6594a5

VMwareでの導入

#PYNQ_flow #Vivado_flow #performance
Best CPU/RAM recommendation for Vivado (Logic and High-level Synthesis)
https://forums.xilinx.com/t5/General-Technical-Discussion/Best-CPU-RAM-recommendation-for-Vivado-Logic-and-High-level/td-p/819755

> So you better get the CPU with the fastest single core performance.

https://www.cpubenchmark.net/singleThread.html

> with i7 4790K:54 minutes. On i9 7900X: 41 minutes.

コア数を減らして、高速なCPUがFPGA開発向きのようだ

#PYNQ_flow #Vivado_flow
Why do I need to run "Create HDL Wrapper..."
https://www.centennialsoftwaresolutions.com/post/why-do-i-need-to-run-create-hdl-wrapper

> This post lists why a Vivado IP integrator a block diagram must be wrapped in an HDL wrapper, short answer: "because a BD (block design) cannot be synthesized directly."

#PYNQ_flow #Vivado_flow

AR 64113
シミュレーション セット内で別の最上位を選択する方法
https://japan.xilinx.com/support/answers/64113.html

#PYNQ_flow #Vivado_flow

2017-06-11
Vivado number of Threads more than 8 Solution
https://forums.xilinx.com/t5/Design-Entry/Vivado-number-of-Threads-more-than-8-Solution/td-p/813093

#PYNQ_flow #AMD #performance

Anyone has built a new Ryzen system and compiled the design?
https://www.reddit.com/r/FPGA/comments/ch4h3e/anyone_has_built_a_new_ryzen_system_and_compiled/

Ryzen 2700 + Vivadoで使った例はある

boards - board specific source code, including the Vivado project sources for the base overlay

#PYNQ_flow #Vivado_flow
Tutorial: Rebuilding the PYNQ base overlay
https://discuss.pynq.io/t/tutorial-rebuilding-the-pynq-base-overlay/61

Vivado 2018.2でのbase overlayのrebuild

#Ultra96_flow #setup

Getting started with installing v2.5 PYNQ on Ultra96 v1 or v2
https://discuss.pynq.io/t/getting-started-with-installing-v2-5-pynq-on-ultra96-v1-or-v2/573

#PYNQ_flow #ZynqBerry

- axis_fb_conf_v1.0 (Pre-Production)
- Video IO to HDMI TMDS Interface v1.0 (Beta)

ZynqBerry向けの独自IP coreのようだ

#PYNQ_flow #ZynqBerry
ZynqBerry用Block Design
vidoe_out用のパッケージ?内のIP

- AXI Video Direct Memory Access
- Clocking Wizard
- axis_fb_conv_v1.0 (Pre-Production)
- Video Timing Controller
- AXI4-Stream to Video Out
- AXI Interconnect
- Video IO to HDMI TMDS Interface v1.0 (Beta)